Low-Noise and Low-Voltage Circuit Techniques for CMOS Analog Design

1. Introduction A system on chip (SoC), which has various functions on a LSI, has been developed for a variety of applications by the submicron technologies. Especially, implantable and/or attachable neural sensor chips, which are implemented by the SoC, attract a lot of interest [1]. The neural sensor chip, which includes with a low-noise amplifier, analog-to-digital converter (ADC), transceiver, and so on, needs low-voltage and low-power operation from the point of view as a long-term operation. However, there are many issues for realizing the neural sensor chip utilizing the sub 0.1 μm technologies [2]. One of the issues is a decreasing of the supply voltage. In the low supply voltage, the CMOS analog switch cannot transmit an intermediate voltage level due to increasing the ON resistance of the analog switch. It makes the operation of sample-and-hold difficult in the ADC which is an essential circuit block for realizing the sensor chip. Other issues are the variability of MOSFETs and increasing low-frequency (1/f) noise. The low-noise amplifier for detecting very small neural signals with μV range is one of the most significant circuits in the sensor chip; however, the detection of the small signals becomes difficult by these issues. This paper presents low-noise and low-voltage circuit techniques for CMOS analog design. These are low-voltage circuit technique utilizing the switched op-amp and grounded switch, and the low-noise circuit techniques of autozero and chopper stabilization operating in the low supply voltage.